ATPG testing is typically used to detect faults, e.g. stuck-at faults, transition faults, in a semiconductor device. Moreover, when the logic to be tested is at the output of a memory, the testing of such logic (called shadow logic from now on) has an associated complexity. FIG. 1 is a block diagram 100 illustrating a simplified test scenario. During an ATPG test mode, in order to get a particular value OR transition on memory output Node2, the most basic way is to perform a write operation of a particular data on a memory address followed by reading it out to get the desired transition. This effectively doubles the number of cycles for each kind of transition on the memory output Node2. To avoid performing a write operation followed by a read operation, some flexibility is allowed to provide the same set of data on the data pins of the memory, as is desired in a particular transition, and make it available at the memory output Node2, hence resulting in the desired value/pattern at the memory output (Node2).
FIG. 2 is a block diagram 200 illustrating a prior art approach for shadow logic testing. In this approach, also known as an external memory bypass implementation, a test pattern generator and a multiplexer MUX are coupled between clock node CK and logic circuit Logic2, independent of logic circuit Logic1 and the memory. Thus, this approach can test the shadow logic at logic circuit Logic2 without accessing the memory, and is capable of detecting stuck-at faults in logic circuit Logic2. However, there is no overall matching between the propagation delay through the test pattern generator (Tdpg) and the actual functional path delay (Taa+Td1). Even if they are reasonably matched under a particular process, voltage, and temperature (PVT) condition, they may be different under different other conditions, thus possibly leading to either under/over-testing with respect to transition faults in shadow logic circuit Logic2. Also, it may not be possible to detect transition faults appearing because of the memory access path (logic circuit Logic1 and Memory). Furthermore, the introduction of the multiplexer MUX on the memory output may not be the most optimum option and may lead to a performance penalty.
FIG. 3 is a block diagram 300 illustrating another prior art approach for shadow logic testing. This approach, also known as the internal asynchronous bypass implementation, is similar to the approach shown in FIG. 2, except that the multiplexer MUX is now inserted into the memory. This approach is also capable of detecting stuck-at faults in shadow logic Logic2, and is somewhat superior to the approach shown in FIG. 2 because the insertion of the multiplexer into the memory is a custom design that results in a lower timing penalty. However, there is still no matching between the propagation delay through ATPG test path (Tdpg+Tdq) and the actual functional path (now Taa+Td1+Tdq). In addition, this approach suffers the other shortcomings as described above with respect to FIG. 2.
FIG. 4 is a block diagram 400 illustrating a memory read access path according to yet another prior art approach. In this approach, also known as the internal-synchronous-bypass approach, a sequential logic delay circuit is coupled between the reference path and the memory IO. The sequential logic delay circuit may be any circuit which waits for the arrival of a clock signal before transmitting the input data to its output, e.g. a flip flop. The clock signal in this case is the sense amplifier enable. This sequential logic delay element is further coupled to a test pattern generator (not shown). The test pattern generator should also ensure setup/hold time of the data inputs with respect to the memory clock signal CK are respected. For example, the signal from the test pattern generator should arrive at the input of the sequential logic delay element slightly before the sense amplifier enable signal from the reference path arrives at its clock input. Here, the access time in ATPG test mode (Taa_atpg) is substantially the same as that in functional mode (Taa), except for the difference between Td1 and T4, where Td1 is the propagation delay through the sequential delay element introduced, and T4 is the sense amplifier reaction time. This approach may also detect stuck-at faults in logic circuit Logic2, and is somewhat better than the approaches described above, e.g. in terms of timing penalty and fault detection. However, the matching of Td1 with T4 is typically difficult under all process conditions as the respective delay mechanisms are very different, i.e. the sense amplifier delay T4 is a latching action, while Td1 is a pure logic delay.
Referring to FIG. 5, in another prior art approach, multiplexers are inserted at the sense amplifier inputs, one on the bitline BL true (BLT) side and another on the bitline BL bar (BLB) side, and no other sequential logic delay element is used. One input of the multiplexer on the BLT input of the sense amplifier receives signal BLT from the memory cell and the other input receives a buffered data signal from the test pattern generator. Similarly, one input of the multiplexer on the BLB input of the sense amplifier receives signal BLB from the memory cell, and the other input of this multiplexer receives the invert of the data generated by the test pattern generator (data bar). The multiplexers are controlled by the “atpg_enable” control pin of the memory, in such a way that in the normal functional mode of the memory (atpg_enable=0), the multiplexers pass BLT and BLB to the respective sense amplifier inputs, while in ATPG test mode (atpg_enable=1), the multiplexers pass the data and data bar inputs generated by the test pattern generator, to the respective sense amplifier inputs. This approach matches all components of the access time in ATPG test mode, except for the dependency of the sense amplifier reaction time (T4) on the voltage differential at the sense amplifier inputs. Typically, during a read operation, the voltage differential available at the sense amplifier input is in the range of few tens of millivolts to a maximum of a couple of hundred of millivolts, depending on the PVT condition. In this prior art approach, it may become difficult to achieve matching between the voltage differential produced by the memory cell during a read operation and that produced by the buffered data and data bar inputs from the test pattern generator. Often, the buffered data produces a full voltage swing at the sense amplifier input, equal or near to the supply voltage, and under this condition, the sense amplifier does not wait for the arrival of a sense amplifier enable signal from the memory reference path, but transmits the buffered data to the output independent of the sense amplifier enable signal, meaning no matching between Taa & Taa_atpg.